library ieee;
use ieee.std_logic_1164.all;


entity adder_ci_co_ref is

  generic (BW : natural);

  port (
    ci     : in  std_logic;
    da, db : in  std_logic_vector(BW-1 downto 0);
    dout   : out std_logic_vector(BW-1 downto 0);
    co     : out std_logic);

end entity adder_ci_co_ref;


architecture str of adder_ci_co_ref is
  signal c_s : std_logic_vector(0 downto 0);
  signal s_s : std_logic_vector(BW downto 0);
begin

  c_s(0) <= ci;
  s_s    <= std_logic_vector(unsigned('0'&da)+unsigned('0'&db)+unsigned(c_s));

  dout <= s_s(BW-1 downto 0);
  co   <= s_s(BW);

end str;